1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to a boundary scan test circuit and a test method thereof.
2. Related Art
A conventional boundary scan test checks the bonding state between semiconductor integrated circuits, such as, Dynamic Random Access Memories (DRAMs), which have already been mounted to a memory board, as well as the memory board.
The, e.g., DRAMs are often bonded and mounted onto two opposite surfaces of the memory board to form a module, which can then be packaged to form a device that will be referred to hereafter as a “chip”. One of the two surfaces of the memory board can be called a “top”, and the other surface can be called a “bottom.” Chips mounted on the top and bottom surfaces of the memory board are electrically connected to interconnections of the memory board.
The semiconductor chips mounted on the memory board can be electrically connected to the memory board through external connection terminals such as pins. The external connection terminals may perform different functions. The external connection terminals may be connected to each other through the same line, so that the semiconductor chips mounted on the top and bottom surfaces of the memory board cannot be subject to a boundary scan test in the same scheme (sequence).
Hereinafter, a typical boundary scan test circuit 10 will be described with reference to FIG. 1. The boundary scan test circuit 10 includes a first latch unit 3-1 to an Nth latch unit 3-N, and a first flip-flop 4-1 to an Nth flip-flop 4-N.
Referring to FIG. 2, when a scan enable signal ‘SEN’ becomes a high level, a boundary scan test is started. When a control signal ‘SSH’ is a low level, the first to Nth latch units 3-1 to 3-N transmit output data signals received from a plurality of pins DM0, DQ5, DQ4, . . . , and RDQ0 to the first to Nth flip-flops 4-1 to 4-N. Accordingly, the first flip-flop 4-1 to the Nth flip-flop 4-N receive the output data signals from a plurality of pins DM0, DQ5, DQ4, . . . , and RDQ0. When a clock signal ‘SCK’ is enabled, the first flip-flop 4-1 to the Nth flip-flop 4-N store and output the received output data signals. However, in this case, since an output enable signal ‘SOE#’ is disabled at a high level, the data of the Nth flip-flop 4-N is not output as a scan output signal ‘SOUT’.
FIG. 3 is a timing chart showing that the first flip-flop 4-1 to the Nth flip-flop 4-N sequentially outputs data, received on a plurality of pins DM0, DQ5, DQ4, . . . , and RDQ0, as the scan output signal ‘SOUT’.
Whenever the clock signal ‘SCK’ is enabled, the first flip-flop 4-1 to the Nth flip-flop 4-N are driven, so that the output data of the first to (N−1)th latch units 3-1 to 3-(N−1) are sequentially transmitted. When the output enable signal ‘SOE#’ is enabled at a low level, a data signal is output from the lowest pin RDQ0.
FIG. 4 is a schematic view showing the connection state of pins of top and bottom chips installed on both surfaces of a memory board.
Referring to FIG. 4, a signal ‘CS’ is applied to the top chip and a signal ‘CAS’ is applied to the bottom chip through the same line. In addition, the signal ‘CAS’ is applied to the top chip and the signal ‘CS’ is applied to the bottom chip through the same line. Further, signal ‘WDQS0’ is applied to the top chip and signal ‘WDQS1’ is applied to the bottom chip through the same line. Thus, as described above, signals for different functions are applied to pins of the top and bottom chips through the same line. Although it is not shown, in addition to signals ‘CS,’ ‘CAS,’ ‘WDQS0,’ and ‘WDQS1’ a plurality of signals exist that are applied to the top and bottom chip, in some instances at least through the same line.
Accordingly, if the boundary scan test is performed by inputting data signals, according to the sequence of pins of the top chip, signals different from those applied to the top chip are input to the bottom chip, so that the data signal output sequence of the bottom chip is different than the data signal output sequence of the top chip. In order to achieve an identical data signal output sequence of the bottom chip as that from the data signal output sequence of the top chip, an additional test program or another test scheme must be used which may result in an increased test time.